1. Field of the Invention
The present invention relates generally to a planar DMOS power transistor and its manufacturing method and, more particularly, to a scalable planar DMOS transistor structure being fabricated without using critical masking photoresist steps.
2. Description of the Prior Art
A conventional planar DMOS (double-diffused MOS) power transistor comprises a plurality of source regions being formed in a lightly-doped epitaxial semiconductor layer, wherein each of the plurality of source regions is formed to be surrounded by a planar gate region. A typical example can refer to FIG. 1, wherein the planar gate region comprises a doped polycrystalline-silicon layer 103a being formed on a gate-oxide layer 102a by using a first masking photoresist (PR1) step, as shown in FIG. 2A; the source region (SR) comprises a moderately-doped p-base diffusion region 104a being formed in the lightly-doped N− epitaxial silicon layer 101 through a first implantation window as shown in FIG. 2B; a heavily-doped n+ source diffusion ring 105a is formed in a surface portion of the moderately-doped p-base diffusion region 104a through a second implantation window between a patterned photoresist layer (PR2) and the patterned doped polycrystalline-silicon layer 103a by using a second masking photoresist (PR2) step as shown in FIG. 2C; a heavily-doped p+ diffusion region 107c being formed in a middle surface portion of the moderately-doped p-base diffusion region 104a through a contact window surrounded by a patterned interlayer oxide layer 106b by using a third masking photoresist (PR3) step as shown in FIG. 2E; and a source metal layer 108 is formed over the contact window and the patterned interlayer oxide layer 106b. 
From the process steps and their schematic cross-sectional views shown in FIG. 2A through FIG. 2E, it is clearly seen that the second and third masking photoresist steps are critical masking photoresist steps and misalignments are inevitable, especially as source area is scaled down. Moreover, the patterned doped polycrystalline-silicon layer 103a is acted as a gate-interconnection conductive layer; higher gate-interconnection parasitic resistance may reduce switching speed of a planar DMOS power transistor.
It is, therefore, a major objective of the present invention to offer a scalable planar DMOS transistor structure being fabricated without critical masking photoresist steps to eliminate all deterioration effects due to misalignments of critical masking photoresist steps.
It is another objective of the present invention to offer a scalable planar DMOS transistor structure with a scalable source area to minimize cell size of a planar DMOS transistor cell.
It is a further objective of the present invention to offer a scalable planar DMOS transistor structure with a patterned heavily-doped polycrystalline-silicon gate layer being locally silicided with metal silicide layers to reduce gate-interconnection parasitic resistance.